Semiconductor device with wire bond inductor and method

ABSTRACT

A semiconductor device ( 10 ) includes a semiconductor die ( 20 ) and an inductor ( 30, 50 ) formed with a bonding wire ( 80 ) attached to a top surface ( 21 ) of the semiconductor die. The bonding wire is extended laterally a distance (L 30,  L 150 ) greater than its height (H 30,  H 50 ) to define an insulating core ( 31, 57 ). In one embodiment, the inductor is extended beyond an edge ( 35, 39 ) of the semiconductor die to reduce loading.

BACKGROUND OF THE INVENTION

The present invention relates in general to semiconductor devices and,more particularly, to integrated circuits that are formed with asemiconductor die and inductors housed in the same semiconductorpackage.

Electronic system manufacturers continue to demand integrated circuitswith increased levels of functionality and a physically smaller size.The demand is particularly evident with portable wireless communicationsdevices, whose size typically is limited by hundreds of discrete passivecomponents that have not yet been successfully integrated due to theiroperation at frequencies of 2.5 gigahertz or more. High frequencyinductors have proven to be particularly difficult to integrate on asemiconductor die because of the performance degradation resulting fromthe parasitic substrate capacitance and eddy currents.

One previous approach to integrating inductors has been to form planarspiral inductors and their associated circuitry on the samesemiconductor die. However, the quality factor of the planar spiralinductors is low due in part to the parasitic substrate capacitance andeddy currents mentioned above. In addition, the additional processingsteps and large die area occupied by the planar inductors has a highcost that has made this approach uneconomical in many applications.

Another approach has been to house a discrete chip inductor and asemiconductor die into the same integrated circuit package. The chipinductors have a high quality factor but the component placement andsolder reflow processing step needed to mount the inductor also resultin a high overall fabrication cost. Moreover, existing discrete chipinductors have a large physical size that increases the profile of thepackaged integrated circuit and precludes their use in manyapplications.

Hence, there is a need for an integrated circuit and method-ofintegrating inductors that combines a low fabrication cost, smallphysical size and high performance.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is an isometric view of a semiconductor device housed in asemiconductor package with inductors;

FIG. 1A is a side view of a first portion of the semiconductor device;

FIG. 1B is an isometric view of a second portion of the semiconductordevice;

FIG. 2 is an isometric view of the semiconductor device in a firstalternate embodiment;

FIG. 3 is an isometric view of the semiconductor device in a secondalternate embodiment;

FIG. 4 is an isometric view of the semiconductor device in a thirdalternate embodiment;

FIG. 5 is a side view of the semiconductor device after a firstfabrication stage;

FIG. 5A is a side view of the semiconductor device after a secondfabrication stage;

FIG. 5B is a side view of the semiconductor device after a thirdfabrication stage; and

FIG. 6 is a side view of the semiconductor device showing an alternatemethod of fabrication.

DETAILED DESCRIPTION OF THE DRAWINGS

In the figures, elements having the same reference number have similarfunctionality.

FIG. 1 is an isometric view of a semiconductor device configured as anintegrated circuit (IC) 10 that includes a semiconductor die 20 and wirebond inductors 30 and 50 all housed in a semiconductor package 40. Inone embodiment, integrated circuit 10 functions as a high frequencyoscillator for use in a dual-band wireless communications device (notshown). Accordingly, integrated circuit 10 generates a high frequencysignal operating at either about eight hundred megahertz or about 2.4gigahertz.

Semiconductor package 40 includes a die attach flag 42 for mountingsemiconductor die 20. A plurality of leads 44 provide electricalconnections to external circuitry (not shown). A plurality of wire bonds46 and a wire bond 46A are attached between leads 44 and a plurality ofbonding pads 25 to route signals between the external circuitry andsemiconductor die 20. Package 40 includes a molded encapsulant 45 forprotecting integrated circuit 10 from damage and corrosion.

Semiconductor die 20 is a monocrystalline silicon chip with a topsurface 21 formed with a voltage controlled oscillator (VCO) 22 having apair of voltage variable capacitors 23 and 24. Capacitor 23 and inductor30 are connected in parallel to operate as a first tank circuit forsetting the 2.4 gigahertz operating frequency of VCO 22, while capacitor24 and inductor 50 are connected in parallel to operate as a second tankcircuit that establishes the eight hundred megahertz operatingfrequency.

Wire bonds 46 and 46A are standard wire bonds formed between theirrespective attachment points or points of contact between bonding pads25 and leads 44. Each of the wire bonds 46 and 46A are formed using awire bonding tool that attaches or welds the bonding wire to a firstattachment point one of the bonding pads 25. The bonding wire is thenfed through a capillary that moves to a second attachment point on oneof the leads 44. The wire bonding tool is programmed to locate the firstand second attachment points and loop the bonding wire to an optimalheight determined by the physical characteristics of a semiconductordie, package and bonding wire.

In order to make wire bonds on a wide variety of semiconductor packages,wire bond tools have mechanisms capable of three-axis motion, i.e., X-and Y-axis motion as indicated by a reference plane 71 coplanar with topsurface 21, and Z-axis motion perpendicular to plane 71. Modern wirebonding tools are programmed to locate the attachment points and to bondthe wire in a point to point fashion. However, in order to form robustand reliable wire bonds in devices with high pin counts, as well asminimizing wire bond inductance, wire bond tools are programmed withcontrol software that prevents standard wire bonds from deviatinglaterally in an X- or Y-direction from a line between the attachmentpoints. Standard wire bonds are formed with only a vertical or Z-axisdeviation to set the desired the loop height. Consequently, either a topview or a view along the length of a standard wire bond appears as astraight line. For example, if a standard wire bond's attachment pointslie along the X-axis, all of its points will have a Y-value ofsubstantially zero and a top view will appear as a straight line lyingalong the X-axis. This can be seen with wire bond 46A, which appears asa straight line because its attachment points are in a line with theview point of FIG. 1.

Inductor 30 is formed with a bonding wire typically having a circularcross-section and which is attached in a standard fashion to bondingpads 32 and 34. In contrast with wire bonds 46 and 46A, inductor 30 isformed to extend laterally a distance L30 from a line 38 through itspoints of attachment to bonding pads 32 and 34. This lateral projectionachieves a higher value of inductance than a standard wire bond withoutincreasing the physical height of integrated circuit 10. The bondingwire used to form inductor 30 preferably comprises a low resistancemetal suitable for wire bonding such as gold or copper, althoughaluminum or other metals or alloys may be used as well. In oneembodiment, inductor 30 is formed with a bonding wire made of gold andhaving a diameter of about fifty micrometers. Inductor 30 typically hasan inductance value in a range between about 0.5 and 3.0 nanohenries.

Inductor 50 is formed with wirebond wire typically of circularcross-section. Inductor 50 similarly is attached to bonding pads 51 and53 and is formed with a coil 52 around an inductor core 57. To reducethe fabrication cost of integrated circuit 10, inductor 50 typically isformed with a bonding wire of similar composition as inductor 30.However, in a suitable application, the inductor 50 bonding wire mayhave a different diameter or a different material composition. Inductor50 typically has an inductance value greater than about two nanohenries.For inductance values of fifteen or more nanohenries, it may beadvantageous to use an insulated bonding wire to avoid shorts whenforming a large number of closely wound turns.

Inductors 30 and 50 are formed with a wire bond tool whose controlsoftware is modified to take advantage of the inherent X-, Y- and Z-axismotion of the tools mechanism. In the embodiment shown in FIG. 1, thelateral or XY deviation capability results in extending inductor 30laterally past edge 35 of semiconductor die 20. A similar result isobtained for inductor 50, which uses a lateral displacement to form coil52 as well as to extend it past edge 39.

FIG. 1A is a side view of a portion of integrated circuit 10 in theembodiment of FIG. 1 showing inductor 30 in further detail. It can beseen that inductor 30 is formed to project laterally over edge 35 in afashion similar to a cantilever in order to provide a high inductanceand quality factor and a low package profile. Inductor 30 isself-supporting when formed with standard bonding wire material but, ifneeded in a particular application, the material used to form inductor30 may be alloyed or doped with beryllium or other material in order toincrease rigidity and provide a springlike resilience or metal “memory”that maintains its shape and position both during and after bonding.

Because inductor 30 extends laterally over edge 35, it has two locations36 and 37 that lie directly or vertically over edge 35. Inductor 30 isshaped to define an inductor core 31 centered along an axis 30Asubstantially perpendicular to top surface 21 to enclose a magnetic fluxwhen current flows through inductor 30. To achieve a high qualityfactor, core 31 is formed as an insulating core, which is a naturalresult of its fabrication since encapsulant 45 is made with aninsulating molding compound such as a thermoplastic resin or epoxy. Adielectric or insulating core is one with no conductive material lyingwithin. Before curing, the encapsulating material has a low viscosity,so inductor 30 is virtually undisturbed when encapsulating material isintroduced into the package mold. After curing, the encapsulatingmaterial hardens to secure the position and shape of inductor 30. In anembodiment in which integrated circuit 10 is not encapsulated, airprovides an excellent alternate insulating core material.

In order to minimize the loading effects of conductive regions ofsemiconductor die 20, inductor 30 is formed so that its lateral distanceL30 is greater than its height H30 above top surface 21. In oneembodiment, distance L30 is about six hundred micrometers while heightH30 is about two hundred micrometers. Axis 30A typically is formed at adistance from line 38 of about L30/2. For a given inductance value, thisarrangement ensures that axis 30A is sufficiently far from semiconductordie 20 so that little or no parasitic eddy currents flow insemiconductor die 20 that reduce the quality factor. Moreover, theseparation of axis 30A from semiconductor die 20 minimizes parasiticcapacitance and results in a high frequency response.

FIG. 1B is an isometric view showing details of a portion of integratedcircuit 10 and inductor 50. As indicated above, inductor 50 is formedwith coil 52 order to increase its inductance while maintaining a highquality factor and a low package profile. Coil 52 typically has acylindrical contour, but may also have an elliptical or polygonal shapeas well, depending on the fabrication method. Note that in thisembodiment, inductor 50 is extended laterally from a line 54 through itsattachment points on bonding pads 51 and 53. Inductor 50 isself-supporting, but in some applications its bonding wire material maybe alloyed or doped with beryllium or other material to increaserigidity to maintain its shape and position.

As with inductor 30, coil 52 surrounds a dielectric or insulatinginductor core 57 that is substantially centered along an axis 50Arunning parallel to edge 39 and has a composition similar to that ofcore 31. A current I₅₀ through coil 52 develops a magnetic flux in core57 that is centered on axis 50A. Core 57 is an insulating core thattypically comprises either air or encapsulating material, as the casemay be.

A low package profile is achieved by forming inductor 50 so that lateraldistance L50 is greater than height H50 of the constituent bonding wireabove top surface 21. Hence, core 57 is far enough from conductiveregions of semiconductor die 20 so that few parasitic effects degradethe inductor 50 performance. In one embodiment, distance L50 is aboutsix hundred micrometers while height H50 is about two hundredmicrometers. Axis 50A typically is formed parallel to line 54 at adistance of about three hundred micrometers.

FIG. 2 is an isometric view of integrated circuit 10 in an alternateembodiment. This embodiment has similar elements and functionalityexcept that bonding wire inductor 50 is attached across leads 58 and 59.Inductor 50 is electrically coupled to VCO 22 through a pair of bondingwires 71-72 attached between leads 58-59 and bonding pads 51 and 53,respectively. Such lead attachment achieves a low package profile, andthe additional space between inductor 50 and semiconductor die 20 mayfacilitate manufacture with some wire bonding tools. Note that the totalinductance coupled across capacitor 24 includes the inductance ofinductor 50 and the respective inductances contributed by bonding wires71 and 72.

FIG. 3 shows an isometric view of integrated circuit 10 in a secondalternate embodiment where bonding wire inductor 50 is attached betweenbonding pad 53 and lead 58.

FIG. 4 is an isometric view of integrated circuit 10 in a thirdalternate embodiment showing bonding wire inductor 50 with axis 50Alocated directly over line 54 intersecting the attachment points. Inthis embodiment, semiconductor package 40 has a higher profile, but thefabrication of this embodiment of inductor 50 may be easier inparticular package configurations.

FIG. 5 shows a side view of integrated circuit 10 during a first stagein the fabrication of inductor 50. A bonding wire 80 is fed through acapillary 82 of a wire bonding tool. A shaper 86 is fed through aconduit or tube 80 and positioned adjacent to semiconductor die 20 asshown. In one embodiment, shaper 86 and tube 80 are made of a lowfriction material such as Teflon®.

Capillary 82 is programmed to first attach wire 80 to bonding pad 51 andthen feed wire 80 at a shallow angle toward shaper 86, which is in itsextended position in tube 84. Capillary 82 then travels in a circular XYmotion while moving more slowly in a Z-direction to wind bonding wirearound shaper 86 one or more times to form coil 52. The number of turnsor windings is determined by the desired inductance of inductor 50. Notethat coil 52 is wound in a vertical or Z-direction with axis 50Acentered in shaper 86.

FIG. 5A shows a side view of integrated circuit 10 during a second stagein the fabrication of inductor 50. Capillary 82 clamps bonding wire 80while shaper 86 is moved to its retracted position in tube 84,suspending coil 52 adjacent to semiconductor die 20 as shown. The lowfriction material used to form shaper 86 and tube 84 facilitates theretraction of shaper 86 without deforming or disturbing coil 52.

FIG. 5B is a side view of integrated circuit 10 during a third stage inthe fabrication of inductor 50. While clamping bonding wire 80 toprevent further wire feeding, capillary 82 is moved in X-direction topull coil 52 into a horizontal position that extends over semiconductordie 20. Bonding wire 80 is then attached to bonding pad 53 and severedto form inductor 50 as shown.

It can be seen that other embodiments of inductor 50 can be made in asimilar fashion by attaching bonding wire to its first attachment point,winding it around shaper 86 to form coil 52 in a vertical direction andthen pulling coil 52 into a horizontal position for bonding to itssecond attachment point.

FIG. 6 shows integrated circuit 10 at a selected manufacturing stage inan alternative method of forming inductor 50. Bonding wire 80 is heatedand fed through threads 88 interior to capillary 82. The threadsprecondition bonding wire 80 to a spring-like shape so that as bondingwire 80 emerges from capillary 82 and cools, it has the desired shape ofcoil 52. Attachment then proceeds as previously described in conjunctionwith FIG. 5B. With this method, bonding wire 80 preferably is doped withberyllium or a similar material to provide a springlike metal “memory”that retains the threaded shape.

In summary, the present invention provides a structure and method ofmaking a semiconductor device that includes one or more wire bondinductors housed in a semiconductor package along with a semiconductordie. The wire bond inductor is formed with a bonding wire attached to atop surface of a semiconductor die. The bonding wire is extendedlaterally a distance greater than a height of the bonding wire to definean insulating core of the inductor.

The inductor formed in accordance with the invention has a high qualityfactor and a high frequency response while providing a low profilesemiconductor package. While several methods of fabricating coils havebeen disclosed, it should be appreciated that other methods can providea similar wire bond inductor. For example, the inductor can be made byutilizing a precoiled bonding wire that is doped with a material toretain its metal “memory”. The bonding wire is then fed through a wirebonding tool in such a way that it retains its shape during inductorformation. Hence, when a predetermined length of the precoiled bondingwire is fed through a capillary, the wire emerges from the capillaryalready having the shape of a coil.

1. A semiconductor device, comprising: a semiconductor die; and aninductor including a first bonding wire attached to a top surface of thesemiconductor die and extended laterally a distance greater than aheight of the bonding wire to define an insulating core.
 2. Thesemiconductor device of claim 1, wherein the first bonding wire hasfirst and second ends respectively attached to first and second bondingpads on the top surface.
 3. The semiconductor device of claim 2, whereinthe first bonding wire is extended from the first and second bondingpads to vertically overlie an edge of the top surface.
 4. Thesemiconductor device of claim 1, wherein the first bonding wire isformed with a coil that surrounds the insulating core.
 5. Thesemiconductor device of claim 4, wherein first and second ends of thefirst bonding wire are attached to first and second bonding pads,respectively, on the top surface and the coil is formed with a pluralityof turns.
 6. The semiconductor device of claim 5, wherein the firstbonding wire has an inductance greater than about five nanohenries. 7.The semiconductor device of claim 1, further comprising a semiconductorpackage for housing the semiconductor die and the inductor.
 8. Thesemiconductor device of claim 7, wherein the first bonding wire isattached to a first bonding pad of the semiconductor die, furthercomprising a second bonding wire attached between a second bonding padof the semiconductor die and a lead of the semiconductor package.
 9. Thesemiconductor device of claim 7, wherein the semiconductor packageincludes an encapsulant for providing the insulating core and formaintaining a position of the coil.
 10. The semiconductor device ofclaim 1, wherein the first bonding wire provides an inductance and thesemiconductor die includes an oscillator operating at a frequencydetermined by the inductance.
 11. The semiconductor device of claim 10,wherein the frequency is greater than two gigahertz.
 12. Thesemiconductor device of claim 1, wherein the bonding wire has asubstantially circular cross-section.
 13. A semiconductor device,comprising: a semiconductor die; and a bonding wire electrically coupledto the semiconductor die and having a first portion formed in a coilaround a dielectric core and a second portion extending vertically froma surface of the semiconductor device.
 14. The semiconductor device ofclaim 13, wherein the bonding wire is attached to first and secondbonding points defining a line, and an axis of the dielectric core issubstantially parallel to the line.
 15. The semiconductor device ofclaim 14, wherein the axis is substantially parallel to an edge of thesemiconductor die.
 16. The semiconductor device of claim 13, furthercomprising a semiconductor package for housing the semiconductor die andthe bonding wire and having a lead that provides the surface forattaching the bonding wire.
 17. A method of operating an integratedcircuit, comprising the steps of: generating a current on asemiconductor die; and routing the current through a coil of a bondingwire to develop a magnetic flux in a dielectric core.
 18. The method ofclaim 17, wherein the step of routing includes the step of routing thecurrent over an edge of the semiconductor die.
 19. The method of claim17, wherein the step of routing further includes the step of generatingthe magnetic flux along an axis of the dielectric core that issubstantially parallel to a line through the first and second ends ofthe bonding wire.